1. Field of the Invention
The present invention relates to a semiconductor device having a vertical channel and, more particularly, to a semiconductor device having a vertical channel capable of reducing the interface resistance between a gate electrode and a word line and a method of manufacturing the same.
This application claims the benefit of Korean Patent Application No. 10-2006-0012578, filed on Feb. 9, 2006, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Discussion of Related Art
With the increase of integration density of semiconductor devices, the size of a MOS transistor (i.e., the channel length of a MOS transistor), has become smaller and smaller in order to accommodate more devices integrally formed within a defined space. Generally, the integration density of a semiconductor device increases as the channel length of the MOS transistor is reduced. However, as the channel length decreases a short channel effect incidentally occurs such as drain induced barrier lowering (DIBL), hot carrier effect, punch through, or the like. This short channel effect causes the semiconductor device to operate abnormally. In order to prevent short channel effects, various methods have been developed, for example junction region depth reduction, extending the channel length by forming grooves in a channel region.
However, as the semiconductor memory device has high integration density in the gigabit range, a MOS transistor having a channel length less than a critical dimension obtained by photolithography is required. For this reason, it is difficult to utilize a planar type MOS transistor to gigabit memory devices where the source and drain regions are formed on the same plane. To overcome these deficiencies, a vertical channel semiconductor device has been proposed in which source/drain regions are formed over and under a gate electrode to form a vertical channel.
The vertical channel semiconductor device (e.g. a vertical channel MOS transistor) includes an active pillar which extends perpendicularly to a main surface of the semiconductor substrate. The gate electrode is formed around the active pillar and the source/drain regions are formed on top and bottom portions of the active pillar in relation to the gate electrode. By forming a vertical channel, the channel length itself is not shortened even though the size of the MOS transistor is reduced. In addition, a bit line is formed in the bottom source/drain region by the gate electrode surrounding the active pillar using a self-aligning method. A word line is also formed such that the word line electrically connects the gate electrodes disposed in the same row or column with respect to one another. However, as the bit line is self-aligned by the gate electrode, the gate electrode and the word line are formed of different materials. As a result, an interface resistance between the gate electrode and the word line increases. If the gate electrode and the word line are formed of the same material, a contact interface exists between the gate electrode and the word line so that the resistance therebetween inevitably increases. That is, the total resistance of the word line of the semiconductor device having the vertical channel may be represented as Equation 1:RT=RWL+RG+RInterface  [Eq. 1]where RWL, denotes the total resistance of the word line, RG denotes the resistance of the gate electrode and RInterface denotes the interface contact resistance between the word line and the gate electrode.
As illustrated in the equation 1, the total resistance RT of the word line is affected by the interface contact resistance RInterface between the word line and the gate electrode. Because the interface contact resistance RInterface is considerably high, this causes a signal delay of the word line. Accordingly, a need exists to develop a semiconductor device having a vertical channel capable of preventing the delay of select signals by reducing the interface contact resistance (RInterface) between the word line and the gate electrode.